The present invention relates to a method and system for testing of Integrated Circuit (IC) devices and more particularly to an enhanced scan partition methodology for testing embedded logic circuits in an IC device.
With the increase in complexity of IC devices, the complexity in testing these devices has also increased. IC devices include one or more embedded logic circuits, each of which needs to be tested for factors such as input and output timing compliance, frequency compliance, path delay faults, connection faults and various types of manufacturing faults. Further, the density of embedded logic circuits designed on IC devices has increased significantly, which has impacted the implementation of test circuits, which require additional chip area. In addition, the embedded logic circuits are sometimes surrounded by various peripheral and I/O circuits, making it difficult to include additional test circuits and making some of the input/output (I/O) terminals of the embedded logic circuits inaccessible by the test circuitry. Further, multiple embedded logic circuits may be integrated on the same IC device, further increasing the complexity of the system. Thus, simple connectivity testing is no longer adequate.
In recent years, scan partitioning has been used for testing embedded logic circuits, including SoC (System on Chip) designs. During testing, the embedded logic circuit being tested is operated in a test mode. In the test mode, the internal connections between the logic devices (such as flip-flops) of the embedded logic circuit are different from their connections in a functional mode. A conventional method of testing the embedded logic circuits of the IC device by scan partitioning is by using scan wrappers. A scan wrapper is a logic circuit that includes a plurality of flip-flops and one or more multiplexers. This allows access and hence the testing of otherwise inaccessible terminals/ports of the internal logic devices/flip-flops of the embedded logic circuits of the IC device.
FIG. 1 is a block diagram illustrating a conventional IC device 100 including circuitry for testing an embedded logic circuit using scan wrappers. The IC device 100 includes a plurality of logic devices 102a, 102b, 102c, . . . , 102i (collectively 102) and a plurality of scan registers 104a, 104b, . . . , 104l (collectively 104) that are combined to form an embedded logic circuit of the IC device 100. To facilitate testing of the embedded logic circuit, two scan partitions A and B are identified to independently test the logic devices 102 in each of the scan partitions A and B. The scan registers 104 are used for testing the embedded logic circuit formed by the logic devices 102. Two or more of the scan registers 104 are stitched into a scan chain such that each of the scan partitions A and B includes a plurality of scan chains. The scan partition A includes scan chains 1 and 2. Similarly, scan partition B includes scan chains 3 and 4. A logic data input S1 provides functional data to the first scan register (Mux D flip-flop) 104a and a logic data output S4 provides a functional data output of a functional path. Similarly, logic data inputs S2 and S3 provide functional data to the scan registers 104b and 104c and the logic data outputs S5 and S6 provide functional data outputs of their respective functional paths. The scan registers 104 are connected in a scan chain such that the output of a scan register is connected to the scan input of the next register and so on. As illustrated in FIG. 1, a scan data input I1 provides input scan data to a scan register 104a of the scan chain 1 and a scan data output O1 provides scan data out from the last scan register 104c of the scan chain 1. The output of the scan register 104a is the scan input for the next scan register 104b and so on. Similarly, scan data inputs I2, I4, and I5 provide input scan data to the scan registers 104g and 104j and scan data outputs O2, O4, and O5 provide scan data out from the last scan registers 104f, 104i, and 104l of their respective scan chains. The output ports of the scan registers of a scan chain of the scan partition A are connected with the input ports the scan registers of a scan chain of the scan partition B through a plurality of scan wrappers 106a, 106b, . . . , 106c (collectively 106) such that no node goes untested. In accordance with the conventional method of testing using scan wrappers, the scan wrappers 106 are active only when the IC device 100 is in the test mode. During the functional mode, the scan wrappers are inactive.
There are various disadvantages of using scan wrappers for testing the embedded logic circuit of the IC device 100, such as loss of transition coverage across partitions, area overhead due to additional and redundant logic, false yield loss on the scan wrapper chain, and implementation complexities in logical integration. FIG. 1 illustrates one of the disadvantages associated with the loss of transition coverage during at-speed test due to a redundant logic associated with scan wrappers 106. A test path 108 associated with the circuitry tested by the scan wrapper 106b during at-speed test of the circuitry at the interface of scan partition A and scan partition B is shown. Similar test paths are associated with the other scan wrappers 106a and 106c. FIG. 1 also illustrates a functional path 110 between the scan partitions A and B. As depicted in FIG. 1, there is a loss of transition coverage when the scan wrapper is implemented for testing the transition path between scan partitions A and B.
In view of the foregoing, it would be desirable to provide an IC device in which the embedded logic circuits can be tested with complete transition coverage across partitions. Further, it would be desirable that the IC device be tested for any manufacturing-induced defects that prevent proper functioning of the logical components or prevent compliance with functional timing specifications. In addition, the IC device should not have additional area overhead due to redundant logic of the scan wrappers. The logical implementation of the test circuit should have reduced complexity and the IC device should not have additional delay when the embedded logic circuit operates in the functional mode.